1. Field of the Invention
This invention relates to an integrated Schottky barrier diode chip made of a compound semiconductor for use in a high frequency circuit, specifically to an integrated Schottky barrier diode chip that includes an insulating region electrically separating portions of a diode of the chip, and a manufacturing method thereof.
2. Description of the Related Art
The demand for high frequency devices has been increasing in recent years because of the worldwide expansion of the portable telephone market as well as the increased demand for digital satellite receiving/sending equipment. Many of these devices utilize a field effect transistor (FET) made of a compound semiconductor, such as gallium arsenide (GaAs), which is suitable for use in a high frequency range. Typical example of such devices include a monolithic microwave integrated circuit (MMIC) that integrates the FETs, a local oscillation FET and a GaAs-based Schottky barrier diode that is used for sending/receiving station in wireless communication.
FIG. 1A is a plan view of a conventional integrated Schottky barrier diode chip, and FIG. 1B is its equivalent circuit. This type of integrated Schottky barrier diode is referred to as a Tee type, and has two Schottky barrier diodes 40a, 40b integrated in a chip. This chip also has a common electrode 36a and its related terminal 34, a cathode electrode 36b and its related terminal 35, and an anode electrode 36c and its related terminal 32. These electrodes 36a, 36b, 36c are indicated by the areas encircled by unevenly broken lines in the figure.
The two Schottky barrier diodes 40a, 40b share the common electrode 36a. In other words, the common electrode 36a serves as a cathode electrode of the Schottky barrier diode 40a, the anode of which is the anode electrode 36c, and serves as an anode of the Schottky barrier diode 40b, the cathode of which is the cathode electrode 36b. The terminals are the areas of the corresponding electrodes that are used for external connection. Typically, those are the areas for wire bonding, and indicated by the circles in FIG. 1A.
This configuration provides a circuit shown in FIG. 1B. Namely, the cathode of the Schottky barrier diode 40a, the anode of which is the anode terminal 32, is connected to the anode of the Schottky barrier diode 40b, the cathode of which is the cathode terminal 35.
FIG. 2 is a cross-sectional view of the integrated Schottky barrier diode chip of FIG. 1A. This cross-section is along the arrow in FIG. 1 and intersects operation areas of the two diodes. An n+ epitaxial layer 22 (Si+5xc3x971018 cmxe2x88x923) is disposed on an undoped GaAs substrate 21 and has a thickness of about 6 xcexcm. An n epitaxial layer 23 (Si+1.3xc3x971017 cmxe2x88x923) is disposed on the n+ epitaxial layer 22 and has a thickness of about 350 nm. This n epitaxial layer 23 serves as an operation layer of the Schottky barrier diodes. An ohmic electrode 28 is a disposed directly on the n+ epitaxial layer 22 and forms an ohmic contact with the n+ epitaxial layer 22. This first metal layer is made of a AuGe/Ni/Au composite metal layer. A second metal layer 33, made of Ti/Pt/Au composite layer, forms a Schottky contact with the n epitaxial layer 23 in a Schottky contact region 31a of the anode portion of the diode, and forms a contact with the ohmic electrode 28 in the cathode portion of the diode. A third metal layer 36 is a Au metal layer, which is formed by plating using the second metal layer 33 as a base electrode, and completely covers the second metal layer 33. Portions 36a, 36b, 36c of the third metal layer 36 serve as the common electrode 36a, the cathode electrode 36b and the anode electrode 36c, respectively.
The Schottky contact region 31a has a circular shape with a diameter of about 10 xcexcm, as shown in FIG. 1. The first metal layer 28 surrounds the Schottky contact region 31a. The first and second metal layers are formed by vapor depositing the constituent metals separately. In the terminal areas 32, 34, 35 of the corresponding electrodes 36c, 36a, 36b, a lead wire is bonded to the electrode surface as shown by reference numerals 32, 34 and 35 in FIG. 2.
In the configuration of FIG. 2, the Schottky barrier diode on the left 40b has the cathode electrode 36b, which serves a cathode of this left diode and the common electrode 36a, which serves as an anode of this left diode, and the Schottky barrier diode on the right 40a has the anode electrode 36c, which serves an anode of this right diode and the common electrode 36a, which serves as a cathode of this right diode. Accordingly, the common electrode 36a works as an anode electrode of the diode 40b and a cathode electrode of the diode 40a. Furthermore, the second metal layer 33 on the Schottky contact regions 31a is at an anode voltage, and the n+ and n epitaxial layers are at a cathode voltage. In this structure, a polyimide layer 30 is required as an insulating layer under the second and third metal layers 33, 36, which are at the anode voltage, at locations in which the metal layers 33, 36 intersect the portions of the epitaxial layers 22, 23, which are at the cathode voltage. The thickness of the polyimide layer 30 needs to be as much as 6-7 xcexcm because this intersection area is large and the resultant parasitic capacitance must be reduced by increasing the thickness. Polyimide is used as the insulating layer because it has a low dielectric constant and suitable for a thick layer formation.
Furthermore, this configuration needs a trench 26 that separates the portions of the epitaxial layers 22, 23, which are at the cathode voltage, from the portions of the epitaxial layers 22, 23, which are at the anode voltage. This is an inevitable requirement when more than two diodes are formed in one chip. The trenches 26 reach the undoped gallium arsenide substrate 21, and are filled with the same polyimide used for the polyimide layer 30. The ohmic electrode 28 needs to form a direct contact with the n+ epitaxial layer for reducing the associated electric resistance. For this reason, a mesa etching is required to expose the n+ epitaxial layer 22 that is covered by the n epitaxial layer 23. The n epitaxial layer 23 at the Schottky contact region is also required to be etched to precisely the thickness of 250 nm for good electric characteristics.
However, the Schottky barrier diode of the conventional configuration described above has a few disadvantages. First, further size reduction of the device is difficult because such a configuration needs a large positional error margin for absorbing mask misplacement during manufacturing due to the tall polyimide layer (6-7 xcexcm) and the deep trenches (15 xcexcm). Second, the trench structure requires an additional process step exclusively designed for trench formation, which needs to be added to a manufacturing method of a discrete device.
This invention is directed to an integrated Schottky barrier diode chip that is smaller and is fabricated by a simpler process than the conventional integrated Schottky barrier diode chip.
The invention provides an integrated Schottky barrier diode chip including a compound semiconductor substrate, an operation layer formed on the substrate, and a plurality of Schottky barrier diodes formed on the substrate. The device also includes an insulating region formed in the operation layer, which electrically separates a first portion of the operation layer of one of the plurality of Schottky barrier diodes from a second portion of the operation layer of that Schottky barrier diodes. The device further includes an impurity region formed in the operation layer, which electrically communicates with one of the first and second portions of the operation layer of that Schottky barrier diode.
The invention also provides an integrated Schottky barrier diode chip that has a first Schottky barrier diode and a second Schottky barrier diode each formed on a compound semiconductor substrate. The device includes an operation layer formed on the substrate, an anode electrode, a cathode electrode and a common electrode. A first insulating region and a first impurity region are formed in the operation layer for the first Schottky barrier diode. A second insulating region and a second impurity region are formed in the operation layer for the second Schottky barrier diode. In this configuration, the first insulating region electrically separates a portion of the operation layer of the first diode that is connected to the anode electrode from a portion of the operation layer of the first diode that is connected to the common electrode, and the second insulating region electrically separates a portion of the operation layer of the second diode that is connected to the common electrode from a portion of the operation layer of the second diode that is connected to the cathode electrode. The first impurity region electrically communicates with the operation layer of the first diode that is connected to the common electrode, and the second impurity region electrically communicates with the operation layer of the second diode that is that is connected to the cathode electrode.
The invention further provides a method of manufacturing an integrated Schottky barrier diode chip having a plurality of Schottky barrier diodes. The method includes forming a plurality of insulating regions on a compound semiconductor substrate by an ion implantation, and forming a Schottky barrier diode on each of the plurality of the insulating regions so that each of the insulating regions electrically separates a first portion of the corresponding diode from a second portion of the corresponding diode.
The invention also provides a method of manufacturing an integrated Schottky barrier diode chip having a plurality of Schottky barrier diodes. The method includes forming an epitaxial layer of a conduction type on an undoped compound semiconductor substrate, forming a plurality of insulating regions in the epitaxial layer by an ion implantation, and forming a Schottky barrier diode on each of the plurality of the insulating regions so that each of the insulating regions electrically separates a first portion of the epitaxial layer of the corresponding diode from a second portion of the epitaxial layer of the corresponding diode.